The simplest and most attractive transistor for high speed and low power GaAs digital integrated circuits is the normally-off or enhancement mode MESFET (E-MESFET). Particularly in very large scale integration (VLSI) applications, the E-MESFET is desirable since, as discussed in the article by K. Suyama et al., entitled "Design and Performance of GaAs Normally-Off MESFET Integrated Circuits", IEEE Transactions on Electron Devices, Vol. ED-27, No. 6, pp. 1092-1097 (June 1980), it enables direct coupling of logic functions and can operate with a single positive power supply. The conventional E-MESFET structure is illustrated in a cross-sectional representation in FIG. 1. It consists of a semi-insulating GaAs substrate 10 having a n.sup.- layer 11 which is formed by either implanting n-type ions or by epitaxial growth. A gate electrode 12 is supported directly on the n.sup.- layer 11 between the heavily doped source 13 and drain 14 and forms a metal-semiconductor (Schottky) contact. The n.sup.- layer 11 is made sufficiently thin, typically as thin as 0.1 .mu.m, and it is lightly doped, typically to a doping density of about 1.times.10.sup.17 atoms/cm.sup.3 to enable the normally-off operation of the device by enabling the depletion region under the Schottky gate 12 to pinch off the channel at zero gate voltage. The source 13 and drain 14 are heavily doped to insure good ohmic contact with their respective alloy contacts 15 and 16 which in turn make electrical contact with metal interconnects 17 and 18, respectively.
Due to its light doping and shallow depth the channel between the source and drain exhibits a high sheet resistivity. Consequently, the prior art MESFET suffers from a large source-drain series resistance which degrades the performance. Also, the heavy doping provided in the source and drain regions, imposes restrictions on device operation. First, it places a limitation on the maximum supply voltage due to the low drain breakdown voltage. Second, it requires the source and drain be spaced sufficiently far away from the gate edges to insure enhancement mode operation. This requirement further compounds the series resistance problem discussed above by increasing the length of the high resistivity channel region. Another disadvantage of the prior art MESFET structure is that it is not amenable to a high level of circuit integration because of the rather large device size.